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Source-Synchronous Networks-On-Chip

Circuit and Architectural Interconnect Modeling

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Paperback / softback
23 August 2016
$219.36
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This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks. The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized. Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic.

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    Product Details
    ISBN-13
    9781493948178
    Author
    Ayan Mandal
    Publisher
    Springer Nature B.V.
    Published
    23 August 2016
    Format
    Paperback / softback

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    $219.36
    Ships in 3-5 business days

    Delivery estimate

    Hurry up! Current stock:

    Source-Synchronous Networks-On-Chip

    $219.36

    Description

    This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks. The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized. Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic.

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