This book introduces a new approach to model and predict substrate parasitic failures in integrated circuits with standard circuit design tools.
The injection of majority and minority carriers in the substrate is a recurring problem in smart power ICs containing high voltage, high current switching devices besides sensitive control, protection and signal processing circuits.
The injection of parasitic charges leads to the activation of substrate bipolar transistors. This book explores how these events can be evaluated for a wide range of circuit topologies. To this purpose, new generalized devices implemented in Verilog-A are used to model the substrate with standard circuit simulators. This approach was able to predict for the first time the activation of a latch-up in real circuits through post-layout SPICE simulation analysis.
Discusses substrate modeling and circuit-level simulation of parasitic bipolar device coupling effects in integrated circuits;
Includes circuit back-annotation of the parasitic lateral n-p-n and vertical p-n-p bipolar transistors in the substrate;
Uses Spice for simulation and characterization of parasitic bipolar transistors, latch-up of the parasitic p-n-p-n structure, and electrostatic discharge (ESD) protection devices;
Offers design guidelines to reduce couplings by adding specific protections.
Parasitic Substrate Coupling in High Voltage Integrated Circuits
RRP:
$227.00
Description
This book introduces a new approach to model and predict substrate parasitic failures in integrated circuits with standard circuit design tools.
The injection of majority and minority carriers in the substrate is a recurring problem in smart power ICs containing high voltage, high current switching devices besides sensitive control, protection and signal processing circuits.
The injection of parasitic charges leads to the activation of substrate bipolar transistors. This book explores how these events can be evaluated for a wide range of circuit topologies. To this purpose, new generalized devices implemented in Verilog-A are used to model the substrate with standard circuit simulators. This approach was able to predict for the first time the activation of a latch-up in real circuits through post-layout SPICE simulation analysis.
Discusses substrate modeling and circuit-level simulation of parasitic bipolar device coupling effects in integrated circuits;
Includes circuit back-annotation of the parasitic lateral n-p-n and vertical p-n-p bipolar transistors in the substrate;
Uses Spice for simulation and characterization of parasitic bipolar transistors, latch-up of the parasitic p-n-p-n structure, and electrostatic discharge (ESD) protection devices;
Offers design guidelines to reduce couplings by adding specific protections.
Standard voltages used in today's ICs may vary from about 1.3V to more than 100V, depending on the technology and the application. High voltage is therefore a relative notion. High Voltage ...
Low-Voltage Low-Power Analog Integrated Circuits brings together in one place important contributions and state-of-the-art research results in this rapidly advancing area. ...
This useful monograph presents a total of seven prototypes: two double-sampled S/H circuits, a time-interleaved ADC, an IF-sampling self-calibrated pipelined ADC, a current steering DAC with a...
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