Testing Concepts.- Design Flow.- Design for Test.- Boundary Scan.- SOC Design for Testability.- System Modeling.- Test Conflicts.- Test Power Dissipation.- Test Access Mechanism.- Test Scheduling.- SOC Test Applications.- A Reconfigurable Power-Conscious Core Wrapper and its Application to System-on-Chip Test Scheduling.- An Integrated Framework for the Design and Optimization of SOC Test Solutions.- Efficient Test Solutions for Core-Based Designs.- Core Selection in the SOC Test Design-Flow.- Defect-Aware Test Scheduling.- An Integrated Technique for Test Vector Selection and Test Scheduling under ATE Memory Depth Constraint.
Introduction to Advanced System-on-Chip Test Design and Optimization
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$415.00
Description
Testing Concepts.- Design Flow.- Design for Test.- Boundary Scan.- SOC Design for Testability.- System Modeling.- Test Conflicts.- Test Power Dissipation.- Test Access Mechanism.- Test Scheduling.- SOC Test Applications.- A Reconfigurable Power-Conscious Core Wrapper and its Application to System-on-Chip Test Scheduling.- An Integrated Framework for the Design and Optimization of SOC Test Solutions.- Efficient Test Solutions for Core-Based Designs.- Core Selection in the SOC Test Design-Flow.- Defect-Aware Test Scheduling.- An Integrated Technique for Test Vector Selection and Test Scheduling under ATE Memory Depth Constraint.
Designing reliable and dependable embedded systems has become increasingly important as the failure of these systems in an automotive, aerospace or nuclear application can have serious consequences...
Design of System on a Chip is the first of two volumes addressing the design challenges associated with new generations of the semiconductor technology. The various chapters are the ...
This book is the second of two volumes addressing the design challenges associated with new generations of semiconductor technology. The various chapters are compiled from tutorials presented at...
Test Resource Partitioning for System-on-a-Chip is about test resource partitioning and optimization techniques for plug-and-play system-on-a-chip (SOC) test automation. ...
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