Design of Wireless Autonomous Datalogger IC's

Abstract I. List of Abbreviations and Symbols. Table of Contents. 1 Introduction. 2 General design aspects of miniaturized low-power dataloggers. 2.1 Introduction. 2.2 Biotelemetry systems. 2.3 Dataloggers. 2.3.1 Sensors. 2.3.2 Signal conditioning. 2.3.3 Data processing. 2.3.4 Power source. 2.3.5 Transceiver. 2.3.6 Packaging. 2.3.7 Smart sensors. 2.4 An injectable transponder example: from prototype to commercial device. 2.4.1 Prototype development: DEVICE 3. 2.4.1.1 General overview. 2.4.1.2 Modes of operation. 2.4.1.3 Practical realization and problems. 2.4.2 Market introduction: DEVICE 4. 2.4.2.1 Modi_cations. 2.4.2.2 Sensor channels. 2.4.2.3 Practical realization. 2.5 Conclusion. 3 Miniaturized datalogger for stress monitoring in oral implants. 3.1 Introduction. 3.2 Clinical background and motivation. 3.3 Measurement methodology. 3.4 External measurement system. 3.5 Strain gauges. 3.6 Specifications of the new miniaturized datalogger. 3.7 Conclusion. 4 Multi-gauge offset-compensated sensor interface chip. 4.1 Introduction. 4.2 Measurement/compensation setup. 4.3 Sensor interface building blocks. 4.3.1 Reference current source. 4.3.1.1 Operating principle. 4.3.1.2 Accuracy and mismatch. 4.3.1.3 Supply-voltage dependence. 4.3.1.4 Temperature dependence. 4.3.1.5 Current mirror inaccuracy. 4.3.2 DAC. 4.3.2.1 DAC requirements. 4.3.2.2 Operating principle and implementation. 4.3.2.3 Derivation and accuracy of the new unit current source. 4.3.3 PROG/SEL-block. 4.3.3.1 Implementation. 4.3.3.2 Programming protocol. 4.3.4 Amplifier. 4.3.4.1 Operating principle. 4.3.4.2 MUX. 4.3.4.3 Finite OTA gain. 4.3.4.4 Settling behavior. 4.3.4.5 Switches. 4.3.4.6 Clock feedthrough and charge injection. 4.3.4.7 Noise. 4.3.4.8 Distortion. 4.3.4.9 CMRR and PSRR. 4.3.5 S/H. 4.3.5.1 Operating principle. 4.3.5.2 Finite OTA gain. 4.3.5.3 Settling behavior. 4.3.5.4 Noise. 4.3.6 ADC. 4.3.6.1 Operating principle. 4.3.6.2 Charge redistribution DAC. 4.3.6.3 Comparator. 4.3.6.4 Reference current source. 4.3.6.5 Settling behavior. 4.3.6.6 Noise. 4.3.7 Oscillator. 4.3.7.1 Operating principle and implementation. 4.3.7.2 Non-overlapping clock generators and -sample. 4.4 Layout. 4.5 Experimental results. 4.5.1 Current consumption. 4.5.2 Clock. 4.5.3 ADC performance. 4.5.4 DAC performance. 4.5.5 Static measurements. 4.5.6 Dynamic measurements. 4.6 Conclusion. 5 Intelligent-datalogger IC with programmable data processing. 5.1 Introduction. 5.2 Principle of operation. 5.2.1 System overview. 5.2.2 Operation modes. 5.3 Digital part and external SRAM. 5.4 Transceiver. 5.5 Instruction set. 5.6 Building blocks of the digital part. 5.6.1 Programming and nulling units. 5.6.2 Data processing unit. 5.6.3 Sampling unit. 5.6.4 Receiving and transmission units. 5.7 Implementation and layout. 5.8 Experimental results. 5.9 Future work: packaging. 5.10 Conclusion. 6 Conclusion. A Transistor dimensions. B Digital error correction of ADC. C Sampling unit. C.1 VHDL code. C.2 Flowchart. List of Publications. Bibliography. Index.